1. Field of the Invention
The present invention relates in general to the separation of a vertical synchronous signal from a composite video signal inputted to a television receiver (TV), and more particularly to a vertical synchronous signal separation apparatus in which the vertical synchronous signal is stably separated from the composite video signal in a digital manner, so that a circuit integration can readily be implemented.
2. Description of the Prior Art
Referring to FIG. 1, there is shown a circuit diagram of a conventional vertical synchronous signal separation apparatus employing an analog manner. As shown in this drawing, the conventional vertical synchronous signal separation apparatus comprises a synchronous signal separation circuit 1 for separating horizontal and vertical synchronous signals from a composite video signal CVS inputted to a TV receiver, an integration circuit 2 for integrating the horizontal and vertical synchronous signals from the synchronous signal separation circuit 1, and a comparator 3 for comparing an output signal from the integration circuit 2 with a reference voltage Vref. The integration circuit 2 includes a resistor R1 and a capacitor C1.
The operation of the conventional vertical synchronous signal separation apparatus with the above-mentioned construction will hereinafter be described with reference to FIG. 1 and FIGS. 2A to 2D, in which FIG. 2A is a waveform diagram of the composite video signal CVS, FIG. 2B is a waveform diagram of the horizontal and vertical synchronous signals from the synchronous signal separation circuit 1, FIG. 2C is a waveform diagram of the output signal from the integration circuit 2 and the reference voltage Vref which are applied to the comparator 3, and FIG. 2D is a waveform diagram of an output signal from the comparator 3.
Upon receiving the composite video signal CVS as shown in FIG. 2A, the synchronous signal separation circuit 1 removes luminance and color signals from the received composite video signal CVS and outputs the remaining horizontal and vertical synchronous signals as shown in FIG. 2B to the integration circuit 2.
In the case where a time constant of the resistor R1 and the capacitor C1 of the integration circuit 2 is adjusted to a vertical equalizing pulse period, a high duration (28 .mu.sec) of each of vertical equalizing pulses is much longer than a low duration (4 .mu.sec) thereof in a first vertical equalizing pulse interval of the horizontal and vertical synchronous signals. In this case, the capacitor C1 of the integration circuit 2 is charged in the first vertical equalizing pulse interval to maintain each high duration in an interval X as shown in FIG. 2C.
On the other hand, in a vertical synchronous pulse interval, a low duration of each of vertical synchronous pulses is much longer than a high duration thereof. As a result, the capacitor C1 of the integration circuit 2 is discharged in an interval Y as shown in FIG. 2C. In a second vertical equalizing pulse interval, the capacitor C1 of the integration circuit 2 is again charged in an interval Z as shown in FIG. 2C in a similar manner to that in the first vertical equalizing pulse interval.
The horizontal and vertical synchronous signals from the synchronous signal separation circuit 1 are processed in the above manner by the integration circuit 2 and then compared with the reference voltage Vref by the comparator 3. If the output signal from the integration circuit 2 is greater than the reference voltage Vref, the output of the comparator 3 is high in level as shown in FIG. 2D. On the contrary, if the output signal from the integration circuit 2 is smaller than the reference voltage Vref, the output of the comparator 3 is low in level as shown in FIG. 2D. Therefore, the vertical synchronous signal is extracted as shown in FIG. 2D.
However, the above-mentioned conventional vertical synchronous signal separation apparatus has a disadvantage in that it has the resistor and the capacitor as individual devices making a circuit integration difficult and, thus, resulting in an increase in the cost. Also, a glitch is present in a portion (A in FIG. 2C) of the reference voltage of the comparator. This glitch results in faulty operations of other systems.